01.01.2012 | Pełny etat | | | Hays PolandDesigns, • Experience with Cadence design environment, • Front-end RTL - VHDL design and top-level verification, • DFT implementation/ verification (Mentor-testKompress), • Timing verification, • Conformal including checks with multiple supply domains, • Preferably physical back-end experience, • Able
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