Top Job | 05.09.2024 | Pełny etat | Wysokie Mazowieckie | Capgemini PolskaAspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below) In deep Floor planning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route Cover all relevant activities
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