16.04.2024 | Pełny etat | Wrocław | BCF Software Sp. z o.o.Or more of experience in ASIC iciency in UVM for at least one year is rience working with complex ASIC and/or large FPGA liarity with IP block verification and multi-clock ng proficiency in Verilog, VHDL, and/or llent English
Zobacz później11.04.2024 | Pełny etat | Katowice | Intel GmbHAnd stress test generation, verification infrastructures and verification and/or debug flows Extensive knowledge of Verilog and SystemVerilog and working knowledge of UVM methodology Good
Zobacz później11.04.2024 | Pełny etat | Kraków | SiliconcrOscillators), high-speed SerDes circuits and fast differential LVDS data interfaces in various CMOS processes from 3 nm to 180 nm for the customers worldwide. For more information, please visit Main responsibilities Generation and verification of real-number Verilog behavioral models for PLLs/SerDes Design
Zobacz później11.04.2024 | Pełny etat | Katowice | Intel GmbHGeneration, verification infrastructures and verification and/or debug flows Extensive knowledge of Verilog and SystemVerilog and working knowledge of UVM methodology Good
Zobacz później11.04.2024 | Pełny etat | Benetel LimitedCapture. To this end, knowledge of 5G and ORAN is desirable but not essential Digital frontend design and verification techniques using SystemVerilog/Verilog Implementing functional and code coverage techniques in simulation Implementation of DSP algorithms for FPGA Using Matlab for all aspects of FPGA
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