05.09.2024 | Pełny etat | Kraków | Capgemini Polska | Resulting in fully functional and performant IP’s/SoC’s YOUR PROFILE Sound basics of system Verilog, and good experience in constrained Random and Coverage Driven Verification with UVM/OVM Experience in creating any UVC components or sequences Basic knowledge on at least two of these AHB/AXI, PCIe/CXL, USB
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